DEC Alpha - Wikipedia. DEC Alpha AXP 2. 10.

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Package for DEC Alpha AXP 2. Alpha AXP 2. 10. 64 bare die mounted on a business card with some statistics. Alpha, originally known as Alpha AXP, is a 6. RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC), designed to replace their 3. VAXcomplex instruction set computer (CISC) ISA. Alpha was implemented in microprocessors originally developed and fabricated by DEC. These microprocessors were most prominently used in a variety of DEC workstations and servers, which eventually formed the basis for almost all of their mid- to- upper- scale lineup.

Several third- party vendors also produced Alpha systems, including PC form factor motherboards. Operating systems that supported Alpha included Open. VMS (previously known as Open.

VMS AXP), Tru. 64 UNIX (previously known as DEC OSF/1 AXP and Digital UNIX), Windows NT (discontinued after NT 4. Windows 2. 00. 0RC1). Compaq, already an Intel customer, decided to phase out Alpha in favor of the forthcoming Hewlett- Packard/Intel Itanium architecture, and sold all Alpha intellectual property to Intel in 2. Hewlett- Packard purchased Compaq later that same year, continuing development of the existing product line until 2.

Alpha- based systems, largely to the existing customer base, until April 2. PRISM was intended to be a flexible design, supporting both Unix- like applications, as well as Digital's existing VMS programs from the VAX after minor conversion.

A new Unix- like. However, development of the workstation was well ahead of the PRISM, and the engineers proposed that they release the machines using the MIPS R2. DEC management doubted the need to produce a new computer architecture to replace their existing VAX and DECstation lines, and eventually ended the PRISM project in 1. By the time of cancellation, however, second- generation RISC chips (such as the newer SPARC architecture) were offering much better price/performance ratios than the VAX lineup. It was clear a third generation would completely outperform the VAX in all ways, not just on cost. Another study was started to see if a new RISC architecture could be defined that could directly support the VMS operating system. The new design used most of the basic PRISM concepts, but was re- tuned to allow VMS and VMS programs to run at reasonable speed with no conversion at all.

The decision was also made to upgrade the design to a full 6. PRISM's 3. 2- bit, a conversion all of the major RISC vendors were undertaking. Internet Download Manager 6 12 Final Build 25 Crack Rar Files more. Eventually that new architecture became Alpha.

The primary Alpha instruction set architects were Richard L. Sites and Richard T. The PRISM's Epicode was developed into the Alpha's PALcode, providing an abstracted interface to platform- and processor implementation- specific features. The main contribution of Alpha to the microprocessor industry, and the main reason for its performance, was not so much the architecture but rather its implementation. The chip designers at Digital continued pursuing sophisticated manual circuit design in order to deal with the overly complex VAX architecture. The Alpha chips showed that manual circuit design applied to a simpler, cleaner architecture allowed for much higher operating frequencies than those that were possible with the more automated design systems.

Hidden Wiki mirror – Deep Web links –.onion urls list – Tor hidden service collection. Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Digital Equipment.

These chips caused a renaissance of custom circuit design within the microprocessor design community. Originally, the Alpha processors were designated the DECchip 2.

The first two digits, . The Alpha was designed as 6. The middle digit corresponded to the generation of the Alpha architecture.

Internally, Alpha processors were also identified by EV numbers, EV officially standing for . The first version, the Alpha 2. EV4, was the first CMOS microprocessor whose operating frequency rivalled higher- powered ECL minicomputers and mainframes. The second, 2. 11. EV5, was the first microprocessor to place a large secondary cache on chip. The third, 2. 12. EV6, was the first microprocessor to combine both high operating frequency and the more complicated out- of- order execution microarchitecture.

The 2. 13. 64 or EV7 was the first high performance processor to have an on- chip memory controller. The unproduced 2. EV8 would have been the first to include simultaneous multithreading, but this version was canceled after the sale of DEC to Compaq. The Tarantula research project, which most likely would have been called EV9, would have been the first Alpha processor to feature a vector unit. Within the computer industry, a joke got started that the acronym AXP meant . Digital intended the architecture to support a one- thousandfold increase in performance over twenty- five years.

To ensure this, any architectural feature that impeded multiple instruction issue, clock rate or multiprocessing was removed. As a result, the Alpha does not have: Branch delay slots.

Suppressed instructions. Byte load or store instructions (later added with the Byte Word Extensions (BWX))Condition codes. Instructions resulting in an overflow, such as adding two numbers whose result does not fit in 6. The carry is generated by performing an unsigned compare on the result with either operand to see if the result is smaller than either operand.

If the test was true, the value one is written to the least significant bit of the destination register to indicate the condition. Registers. It also defined registers that were optional, implemented only if the implementation required them. Lastly, registers for PALcode were defined. The integer registers were denoted by R0 to R3. F0 to F3. 1. The R3. F3. 1 registers were hardwired to zero and writes to those registers by instructions are ignored. Digital considered using a combined register file, but a split register file was determined to be better as it enabled two- chip implementations to have a register file located on each chip and integer- only implementations to omit the floating- point register file containing the floating point registers.

A split register file was also determined to be more suitable for multiple instruction issue due to the reduced number of read and write ports. The number of registers per register file was also considered, with 3.

Digital concluded that 3. This number of registers was deemed not to be a major issue in respect to performance and future growth, as thirty- two registers could support at least eight- way instruction issue. The program counter is a 6. The PC is incremented by four to the address of the next instruction when an instruction is decoded. A lock flag and locked physical address register are used by the load- locked and store- conditional instructions for multiprocessor support. The floating- point control register (FPCR) is a 6.

Alpha implementations with IEEE 7. Data types. Implementations can implement a smaller virtual address space with a minimum size of 4.

Although the unused bits were not implemented in hardware such as TLBs, the architecture required implementations to check whether they are zero to ensure software compatibility with implementations with a larger (or full) virtual address space. Instruction formats. It has six instruction formats. Type. Opcode. Ra. Rb. Unused. 0Function. Rc. Integer operate. Opcode. Ra. Literal.

Function. Rc. Integer operate, literal. Opcode. Ra. Rb. Function. Rc. Floating- point operate. Opcode. Ra. Rb. Displacement. Memory format. Opcode. Ra. Displacement.

Branch format. Opcode. Function. CALL. It contains a 6- bit opcode field, followed by the Ra field, which specifies the register containing the first operand and the Rb field, specifies the register containing the second operand. Next is a 3- bit field which is unused and reserved. A 1- bit field contains a . A 7- bit function field follows, which is used in conjunction with the opcode to specify an operation. The last field is the Rc field, which specifies the register which the result of a computation should be written to.

The register fields are all 5 bits long, required to address 3.

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